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general description the max3394e/max3395e/max3396e bidirectional level translators provide level shifting required for data transfer in a multivoltage system. internal slew-rate enhancement circuitry features 10ma current-sink and 15ma current-source drivers to isolate capacitive loads from lower current drivers. in open-drain systems, slew- rate enhancement enables fast data rates with larger pullup resistors and increased bus load capacitance. externally applied voltages, v cc and v l , set the logic- high levels for the device. a logic-low signal on one i/o side of the device appears as a logic-low signal on the opposite i/o side, and vice-versa. each i/o line is pulled up to v cc or v l by an internal pullup resistor, allowing the devices to be driven by either push-pull or open-drain drivers. the max3394e/max3395e/max3396e feature a tri- state output mode, thermal-shutdown protection, and ?5kv human body model (hbm) esd protection on the v cc side for greater protection in applications that route signals externally. the max3394e/max3395e/max3396e accept v cc volt- ages from +1.65v to +5.5v, and v l voltages from +1.2v to v cc , making them ideal for data transfer between low voltage asic/plds and higher voltage systems. the max3394e/max3395e/max3396e operate at a guaran- teed data rate of 6mbps with push-pull drivers and 1mbps with open-drain drivers. the max3394e is a dual-level translator available in 9-bump ucsp and 8-pin 3mm x 3mm tdfn packages. the max3395e is a quad-level translator available in 12- bump ucsp, and 12-pin 4mm x 4mm tqfn packages. the max3396e is an octal-level translator available in 20- bump ucsp and 20-pin 5mm x 5mm tqfn packages. the max3394e/max3395e/max3396e operate over the extended -40? to +85? temperature range. applications multivoltage bidirectional level translation spi, microwire, and i 2 c level translation open-drain rise-time speed-up high-speed bus fan-out expansion cell phones telecom, networking, servers, raid/san features 15kv esd protection on i/o v cc_ lines bidirectional level translation without direction pin i/o v l_ and i/o v cc_ 10ma sink-/15ma source- current capability slew-rate enhancement circuitry supports larger capacitive loads or larger external pullup resistors 6mbps push-pull/1mbps open-drain guaranteed data rate wide supply-voltage range: operation down to +1.2v on v l and +1.65v on v cc low supply current in tri-state output mode (3a typ) low quiescent current thermal-shutdown protection ucsp, tdfn, and tqfn packages max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry ________________________________________________________________ maxim integrated products 1 19-3884; rev 2; 2/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. 12 34 8 7 6 5 v l i/o v l 1 i/o v l 2 gnd *connect exposed pad to ground *ep i/o v cc 2 i/o v cc 1 en v cc max3394e tdfn top view (leads on bottom) + pin configurations ordering information part pin-package pkg code max3394e eta+t 8 tdfn-ep** t833-1 max3394eebl+t 9 ucsp b9-5 max3395e etc+ 12 tqfn-ep** t1244-4 max3395eebc+t 12 ucsp b12-1 max3396e ebp+t* 20 ucsp b20-1 max3396eetp+* 20 tqfn-ep** t2055-4 note: all devices specified over the -40? to +85? operating range. + denotes lead(pb)-free/rohs-compliant package. * future product?ontact factory for availability. **ep = exposed paddle. pin configurations continued at end of data sheet. selector guide appears at end of data sheet.
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.) v cc ......................................................................... -0.3v to +6v v l ............................................................................ -0.3v to +6v i/o v cc_ ...................................................... -0.3v to v cc + 0.3v i/o v l_ ........................................................... -0.3v to v l + 0.3v en ........................................................................... -0.3v to +6v short-circuit duration i/o v l_ , i/o v cc_ to gnd ..... continuous maximum continuous current ........................................ ?0ma continuous power dissipation (t a = +70?) 8-pin tdfn (derate 18.2mw/? above +70?) ........ 1455mw 9-bump ucsp (derate 4.7mw/? above +70?) ........ 379mw 12-pin tqfn (derate 16.9mw/? above +70?) ........1349mw 12-bump ucsp (derate 6.5mw/? above +70?) ..... 519mw 20-pin tqfn (derate 20.8mw/? above +70?) ........1667mw 20-bump ucsp (derate 10.0mw/? above +70?) .....800mw operating temperature range ......................... -40? to +85? storage temperature range ........................... -65? to +150? junction temperature .....................................................+150? bump temperature (soldering) ...................................... +235? lead temperature (soldering, 10s) ............................... +300? electrical characteristics (v cc = +1.65v to +5.5v, v l = +1.2v to v cc ; c iovl 15pf, c iovcc 15pf; t a = -40? to +85?, unless otherwise noted. typical val- ues are at t a = +25?.) (note 1) parameter symbol conditions min typ max units power supply v l supply range v l 1.2 v cc v v cc supply range v cc 1.65 5.50 v max3394e 150 max3395e 300 supply current from v cc i cc i/o lines internally pulled up max3396e 600 ? max3394e 30 max3395e 30 supply current from v l i l i/o lines internally pulled up max3396e 30 ? v cc tri-state supply current i cc-3 en = gnd, t a = +25? 3 6 ? v l tri-state supply current i l-3 en = gnd, t a = +25? 0.7 2 a logic i/o i/o v l _ input-voltage high threshold v ihl 0.7 x v l v i/o v l _ input-voltage low threshold v ill 0.3 x v l v i/o v l _ internal pullup dc resistance r l en = v cc or v l 51020k ? i/o v l _ source current during low-to-high transition i ihl v l = +1.2v 15 ma i/o v l _ sink current during high- to-low transition i ill v cc = +1.65v 10 ma
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +1.65v to +5.5v, v l = +1.2v to v cc ; c iovl 15pf, c iovcc 15pf; t a = -40? to +85?, unless otherwise noted. typical val- ues are at t a = +25?.) (note 1) parameter symbol conditions min typ max units i/o v l _ low-to-high transition threshold v l-th v cc = +3.3v, v l = +1.8v 0.3 x v l 0.5 x v l v i/o v l _ sink current = 5ma, v ilc = 0v 0.25 i/o v l _ output-voltage low v oll i/o v l _ sink current = 10ma, v ilc 0.4v or 0.2 x v l v ilc + 0.4v v i/o v l _ tri-state output leakage current en = gnd, t a = +25? -1 +1 ? i/o v cc _ input-voltage high threshold v ihc (note 2) 0.7 x v cc v i/o v cc _ input-voltage low threshold v ilc (note 2) 0.3 x v cc v i/o v cc _ internal pullup dc resistance r cc en = v cc or v l 51020k ? i/o v cc _ source current during low-to-high transition i ihcc v cc = +1.65v 15 ma i/o v cc _ sink current during high-to-low transition i ilcc v cc = +1.65v 10 ma i/o v cc _ low-to-high transition threshold v cc-th v cc = +3.3v, v l = +1.8v 0.3 x v cc 0.5 x v cc v i/o v cc _ sink current = 5ma, v ill = 0v 0.25 i/o v cc _ output-voltage low v olc i/o v cc _ sink current = 10ma, v ill 0.4v or 0.2 x v l v ill + 0.4v v i/o v cc _ tri-state output leakage current en = gnd, t a = +25? -1 +1 ? en input-voltage high threshold v ihe 0.7 x v l v en input-voltage low threshold v ile 0.3 x v l v en pin input leakage current t a = +25? -1 +1 ? esd protection i/o v cc _ esd protection c vcc = 1?, human body model ?5 kv
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry 4 _______________________________________________________________________________________ timing characteristics (v cc = +1.65v to +5.5v, v l = +1.2v to v cc ; c iovl 15pf, c iovcc 15pf; t a = -40? to +85?, unless otherwise noted. typical val- ues are at t a = +25?.) (note 1) parameter symbol conditions min typ max units push-pull driver, figure 1 50 i/o v cc _ rise time t rvcc open-drain driver, internal pullup, figure 2 500 ns push-pull driver, figure 1 50 i/o v cc _ fall time t fvcc open-drain driver, internal pullup, figure 2 50 ns push-pull driver, figure 3 50 i/o v l _ rise time t rvl open-drain driver, internal pullup, figure 4 500 ns push-pull driver, figure 3 50 i/o v l _ fall time t fvl open-drain driver, internal pullup, figure 4 50 ns push-pull driver, figure 1 50 t i/ovl-vcc open-drain driver, internal pullup, figure 2 600 push-pull driver, figure 3 50 propagation delay t i/ovcc-vl open-drain driver, internal pullup, figure 4 600 ns propagation delay after en t en push-pull or open-drain driver, figure 5 5 ? push-pull driver 5 channel-to-channel skew t skew open-drain driver, internal pullup 100 ns push-pull driver, figures 1, 3 6 maximum data rate open-drain driver, internal pullup, figures 2, 4 1 mbps note 1: all units are 100% production tested at t a = +25?. limits over the operating temperature range are guaranteed by design and not production tested. note 2: during a low-to-high transition, the threshold at which the i/o changes state is the lower of v ill and v ilc since the two sides are internally connected by an internal switch while the device is in the logic-low state.
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry _______________________________________________________________________________________ 5 typical operating characteristics (v cc = +2.5v, v l = +1.8v, c l = 15pf, t a = +25?, unless otherwise noted.) v cc supply current vs. supply voltage max3394e?6e toc01 v cc supply voltage (v) v cc supply current (ma) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0.5 1.0 1.5 2.0 2.5 3.0 0 1.5 5.5 v l = +1.2v driving i/o v l 1mbps open-drain 6mbps push-pull v l supply current vs. supply voltage max3394e?6e toc02 v l supply voltage (v) v l supply current (ma) 4.5 4.0 3.5 3.0 2.5 2.0 0.5 1.0 1.5 2.0 2.5 3.0 0 1.5 5.0 v cc = +5.0v driving i/o v l 1mbps open-drain 6mbps push-pull v cc supply current vs. temperature max3394e?6e toc03 temperature ( c) v cc supply current (ma) 60 35 10 -15 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -40 85 driving i/o v l 1mbps open-drain 6mbps push-pull v l supply current vs. temperature max3394e?6e toc04 temperature ( c) v l supply current (ma) 60 35 10 -15 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0 -40 85 driving i/o v l 1mbps open-drain 6mbps push-pull 0 1.5 1.0 0.5 2.0 2.5 3.0 040 30 10 20 50 60 70 80 90 100 max3394e-96e toc05 capacitive load (pf) v cc supply current (ma) v cc supply current vs. capacitive load driving i/o v l 6mbps push-pull 1mbps open-drain 0 0.2 0.1 0.4 0.3 0.6 0.5 0.7 0.9 0.8 1.0 0203040 10 50 60 70 90 80 100 max3394e-96e toc06 capacitive load (pf) v l supply current (ma) v l supply current vs. capacitive load driving i/o v l 6mbps push-pull 1mbps open-drain 0 100 50 200 150 300 250 350 450 400 500 0203040 10 50 60 70 90 80 100 max3394e-96e toc07 capacitive load (pf) rise time (ns) open-drain rise time vs. load capacitance driving i/o v l driving i/o v cc open-drain fall time vs. load capacitance max3394e?6e toc08 load capacitance (pf) fall time (ns) 90 80 70 60 50 40 30 20 10 5 10 15 20 25 30 0 0 100 driving i/o v cc driving i/o v l push-pull rise time vs. capacitive load max3394e?6e toc09 capacitive load (pf) rise time (ns) 90 80 70 60 50 40 30 20 10 5 10 15 20 25 30 0 0100 driving i/o v cc driving i/o v l
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v cc = +2.5v, v l = +1.8v, c l = 15pf, t a = +25?, unless otherwise noted.) 0 4 2 8 6 12 10 14 040 20 60 80 10 50 30 70 90 100 max3394e-96e toc10 load capacitance (pf) fall time (ns) push-pull fall time vs. load capacitance driving i/o v l driving i/o v cc 0 15 10 5 20 25 30 040 30 10 20 50 60 70 80 90 100 propagation delay vs. load capacitance max3394e-96e toc11 load capacitance (pf) propagatin delay (ns) driving i/o v l open-drain t pdhl t pdlh 0 4 2 8 6 12 10 14 18 16 20 0203040 10 50 60 70 90 80 100 max3394e-96e toc12 load capacitance (pf) propagation delay (ns) driving i/o v cc open-drain propagation delay vs. load capacitance t pdhl t pdlh propagation delay vs. load capacitance max3394e?6e toc13 load capacitance (pf) propagation delay (ns) 90 80 60 70 20 30 40 50 10 5 10 15 20 25 30 35 40 45 50 0 0100 t pdhl driving i/o v l push-pull t pdlh 0 4 2 8 6 12 10 14 18 16 20 0203040 10 50 60 70 90 80 100 max3394e-96e toc14 load capacitance (pf) propagation delay (ns) driving i/o v cc push-pull see figure 3 propagation delay vs. load capacitance t pdhl 40ns/div (driving i/o v l , v cc = +2.5v, v l = +1.8v, c l = 15pf, data rate = 6mbps) i/o v cc 1v/div i/o v l 1v/div max3394e-96e toc15 200ns/div (driving i/o v l , v cc = +5.0v, v l = +3.3v, c l = 100pf, data rate = 1mbps) max3394e-96e toc16 i/o v cc 2v/div i/o v l 2v/div 200ns/div (driving i/o v l , v cc = +5.0v, v l = +3.3v, c l = 400pf, external 4.7k ? pullups, data rate = 1mbps) max3394e-96e toc17 i/o v cc 2v/div i/o v l 2v/div
detailed description the max3394e/max3395e/max3396e bidirectional level translators provide level shifting required for data transfer in a multivoltage system. internal slew-rate enhancement circuitry features 10ma current-sink and 15ma current-source drivers to isolate capacitive loads from lower current drivers. in open-drain systems, slew- rate enhancement enables fast data rates with larger pullup resistors and increased bus load capacitance. externally applied voltages, v cc and v l , set the logic- high levels for the device. a logic-low signal on one i/o side of the device appears as a logic-low signal on the opposite i/o side and vice-versa. each i/o line is pulled up to v cc or v l by an internal pullup resistor, allowing the devices to be driven by either push-pull or open- drain drivers. max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry _______________________________________________________________________________________ 7 pin description pin max3394e max3395e max3396e tdfn ucsp tqfn ucsp tqfn ucsp name function 1 a111b114d3v cc v cc supply voltage +1.65v v cc +5.5v. bypass v cc to gnd with a 0.1? ceramic capacitor and a 1? or greater ceramic capacitor as close to the device as possible. 2 b1 6 b3 4 a4 en enable input. drive en logic high for normal operation. drive en logic low to force all i/o lines to a high-impedance state and disconnect internal pullup resistors. 3 a2 10 c1 18 c1 i/o v cc 1 i/o 1 referred to v cc 4 a3 9 c2 16 d1 i/o v cc 2 i/o 2 referred to v cc 5 b3 5 b4 13 d4 gnd ground 6 c3 2 a2 20 a1 i/o v l 2 i/o 2 referred to v l 7 c2 1 a1 19 b1 i/o v l 1 i/o 1 referred to v l 8 c1 12 b2 3 a3 v l logic supply voltage +1.2v v l v cc . bypass v l to gnd with a 0.1? or greater ceramic capacitor as close to the device as possible. 3 a3 1 b2 i/o v l 3 i/o 3 referred to v l 4 a4 2 a2 i/o v l 4 i/o 4 referred to v l 7 c4 15 d2 i/o v cc 4 i/o 4 referred to v cc 8 c3 17 c2 i/o v cc 3 i/o 3 referred to v cc 12 c3 i/o v cc 5 i/o 5 referred to v cc 11 d5 i/o v cc 6 i/o 6 referred to v cc 10 c4 i/o v cc 7 i/o 7 referred to v cc 9 c5 i/o v cc 8 i/o 8 referred to v cc 5 b3 i/o v l 5 i/o 5 referred to v l 6 a5 i/o v l 6 i/o 6 referred to v l 7 b4 i/o v l 7 i/o 7 referred to v l 8 b5 i/o v l 8 i/o 8 referred to v l ep ep ep ep exposed pad. connect exposed pad to gnd.
max3394e/max3395e/max3396e the max3394e/max3395e/max3396e feature a tri- state output mode, thermal-shutdown protection, and ?5kv human body model (hbm) esd protection on the v cc side for greater protection in applications that route signals externally. the max3394e/max3395e/max3396e accept v cc volt- ages from +1.65v to +5.5v, and v l voltages from +1.2v to v cc , making them ideal for data transfer between low- voltage asic/plds and higher voltage systems. the max3394e/max3395e/max3396e operate at a guaran- teed data rate of 6mbps with push-pull drivers and 1mbps with open-drain drivers. level translation the max3394e/max3395e/max3396e utilize a trans- mission gate architecture to provide bidirectional level translation between i/o v l _ and i/o v cc _. the trans- mission gate architecture is comprised of a pass-fet, gate-control logic, and slew-rate enhancement circuit- ry. when both i/o v l _ and i/o v cc _ are logic high, the gate-control logic disables the pass-fet, providing 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry 8 _______________________________________________________________________________________ max3394e max3395e max3396e t fvcc t rvcc t i/ovl-vcc i/o v l_ i/o v cc_ 50 ? v l v l v cc 10% 10% 90% 90% 50% 50% 50% 50% v cc c iovcc t i/ovl-vcc v cc en v l i/o v cc i/o v l figure 1. push-pull driving i/o v l_ test circuit and timing max3394e max3395e max3396e t fvcc t rvcc t i/ovl-vcc i/o v l_ i/o v cc_ v l v l v cc 10% 10% 90% 90% 50% 50% 50% 50% v cc c iovcc t i/ovl-vcc i/o v cc v gate v l v cc en v gate figure 2. open-drain driving i/o v l_ test circuit and timing
capacitive isolation between i/o lines. when one or both i/o lines are at a logic-low level, the gate-control logic turns the pass-fet on. when the pass-fet is active, i/o v l _ and i/o v cc _ are connected, allowing the logic-low signal to be expressed simultaneously on both i/o lines. the max3394e/max3395e/max3396e have internal 10k ? (typ) pullup resistors from i/o v l _ and i/o v cc _ to the respective supply voltages, allowing operation with open-drain drivers. internal slew-rate enhancement circuitry accelerates logic-state transitions, maintaining a fast data rate with a higher bus load capacitance. additionally, the 10ma current sink drivers permit the use of smaller external pullup resistors. internal slew-rate enhancement internal slew-rate enhancement circuitry accelerates logic-state changes by turning on mosfets m p1 and m p2 during low-to-high logic transitions, and mosfets m n3 and m n4 during high-to-low logic transitions (see the functional diagram ). during logic-state changes, speed-up mosfets are triggered by i/o line voltage thresholds. mosfets m n3 and m n4 sink 10ma during high-to-low logic transitions. m p1 and m p2 source 15ma during low-to-high logic transitions. slew-rate enhance- ment allows a fast data rate despite large capacitive bus loads, and permits larger external pullup resistors. max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry _______________________________________________________________________________________ 9 max3394e max3395e max3396e t fvl t rvl t i/ovcc-vl i/o v l_ i/o v cc_ v l v l v cc 10% 10% 90% 90% 50% 50% 50% 50% v cc c iovl t i/ovcc-vl i/o v cc v l v cc en 50 ? i/o v l figure 3. push-pull driving i/o v cc_ test circuit and timing max3394e max3395e max3396e t i/ovcc-vl i/o v l_ i/o v cc_ v l v l v cc 10% 10% 90% 90% 50% 50% 50% 50% v cc c iovl t i/ovcc-vl i/o v l v l v cc en t fvl t rvl v gate figure 4. open-drain driving i/o v cc_ test circuit and timing
max3394e/max3395e/max3396e power-supply sequencing the max3394e/max3395e/max3396e require two sup- ply voltages. for proper operation, ensure that +1.65v v cc +5.5v, and +1.2v v l v cc . there are no restric- tions on power-supply sequencing. during power-up or power-down, the max3394e/max3395e/max3396e can withstand either the v l or the v cc supply floating while the other supply is applied. the device will not latch up in this state. tri-state output mode connect en to v l or v cc for normal operation. drive en low to force the max3394e/max3395e/max3396e to a tri-state output mode. in tri-state output mode, all i/o lines are driven to a high-impedance state, and the pass-fet is disabled to prevent current flow between i/o lines. tri-state output mode disables the internal pullup resistors on i/o v l _ and i/o v cc _, and reduces supply current to 3? typ (v cc ) and 0.7? typ (v l ). 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry 10 ______________________________________________________________________________________ max3394e max3395e max3396e i/o v l_ i/o v cc_ v l v l v cc v cc v l v cc en 50 ? r load c iovcc max3394e max3395e max3396e i/o v cc_ v l v l v cc v cc v l v cc en 50 ? r load i/o v l_ en en time time t en t en i/o v cc_ v i/o v l_ v c iovl 0.5v 0.2v (v l < 2v) 0.5v (v l 2v) figure 5. enable test circuit and timing
the high-impedance state of the i/o lines during tri- state output mode facilitates use in multidrop networks. in tri-state output mode, do not exceed (v l + 0.3v) on i/o v l _ or (v cc + 0.3v) on i/o v cc _. thermal-shutdown protection the max3394e/max3395e/max3396e are protected from thermal damage resulting from short-circuit faults. in the event of a short-circuit fault, when the junction temperature (t j ) reaches +125?, a thermal sensor forces the device into the tri-state output mode. when t j drops below +115?, normal operation resumes. 15kv esd protection as with all maxim devices, esd-protection structures are incorporated on all pins to protect against esd encoun- tered during handling and assembly. the i/o v cc _ lines are further protected by advanced esd structures to guard these pins from damage caused by esd of up to ?5kv. protection structures prevent damage caused by esd events in normal operation, tri-state output mode, and when the device is unpowered. after arresting an esd event, max3394e/max3395e/max3396e continue to function without latching up, whereas competing devices can enter a latched-up state and must be power cycled to restore functionality. several esd testing standards exist for gauging the robustness of esd structures. the esd protection of the max3394e/max3395e/max3396e is characterized for the human body model (hbm). figure 6a shows the model used to simulate an esd event resulting from contact with the human body. the model consists of a 100pf storage capacitor that is charged to a high volt- age then discharged through a 1.5k ? resistor. figure 6b shows the current waveform when the storage capacitor is discharged into a low impedance. to ensure full ?5kv esd protection, bypass v cc to ground with a 0.1? ceramic capacitor and an additional 1? ceramic capacitor as close to the device as possible. esd test conditions esd performance depends on a variety of conditions. contact maxim for a reliability report documenting test setup, methodology, and results. applications information power-supply decoupling bypass v l and v cc to ground with 0.1? ceramic capacitors. to ensure full ?5kv esd protection, bypass v cc to ground with an additional 1? or greater ceramic capacitor. place all capacitors as close to the device as possible. open-drain mode vs. push-pull mode the max3394e/max3395e/max3396e are compatible with push-pull (active) and open-drain drivers. for push- pull operation, maximum data rate is guaranteed to 6mbps. for open-drain applications, the max3394e/ max3395e/max3396e include internal pullup resistors and slew-rate enhancement circuitry, providing a maxi- mum data rate of 1mbps. external pullup resistors can be added to increase data rate when the bus is loaded by high capacitance. (see the use of external pullup resistors section.) serial-interface level translation the max3395e provides level translation on four i/o lines, making it an ideal device for multivoltage i 2 c, microwire, and spi serial interfaces. use of external pullup resistors the max3394e/max3395e/max3396e include internal 10k ? pullup resistors. during a low-to-high logic transi- tion, the internal pullup resistors charge the bus capac- max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry ______________________________________________________________________________________ 11 charge-current- limit resistor discharge resistance storage capacitor c s 100pf r c 1m ? r d 1500 ? high- voltage dc source device- under- test figure 6a. human body esd test model i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes figure 6b. hbm discharge current waveform
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry 12 ______________________________________________________________________________________ gnd gnd gnd +1.8v system controller +3.3v system v l v cc i/o v l 1 i/o v l 2 i/o v cc 1 i/o v cc 2 clk data clk data +3.3v +1.8v en en 0.1 f 1 f 0.1 f max3394e typical operating circuit m p2 m p1 m n4 m n3 gate control slew-rate enhancement n-channel pass-fet i/o v l_ i/o v cc_ v l v cc v l v cc functional diagram itance with a characteristic rc charging waveform. when the low-to-high transition threshold (v cc-th or v l- th ) is reached, the rise time accelerators switch on, sourcing 15ma to fully charge the bus capacitance. external pullup resistors reduce the time needed to reach the low-to-high transition threshold, thereby increasing the data rate. in the logic-low state however, external pullup resistors increase the dc current through the internal pass-fet, increasing the output voltage of the device. smart-card interface the max3395e provides level translation for class a, b, and c smart cards. when supply voltage v cc is inter- rupted due to the disconnection of a smart card, the device does not latch up. normal operation resumes upon restoration of the v cc supply voltage. the max3395e provides bidirectional level translation on four i/o lines, making it well suited for buffering and translating 4-wire serial interfaces. ucsp applications information for the latest application details on ucsp construction, dimensions, tape carrier information, pcb techniques, bump-pad layout, and recommended reflow tempera- ture profiles, as well as the latest information on reliabili- ty testing results, go to maxim? web site at www.maxim-ic.com/ucsp to find the application note: ucsp? wafer-level chip-scale package .
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry ______________________________________________________________________________________ 13 123 a b c ucsp ucsp a b c 12 3 4 12 v l 11 v cc 10 i/o v cc 1 4 5 gnd 6en 12 i/o v l 2 3 987 i/o v l 3 i/o v cc 2 i/o v cc 3 i/o v cc 4 max3395e i/o v l 1 i/o v l 4 tqfn top view (bumps on bottom) max3394e v cc i/o v cc 1 i/o v cc 2 i/o v l 1 i/o v l 2 en gnd v l i/o v l 2 i/o v l 4 i/o v l 1 i/o v l 3 v l gnd v cc en max3395e i/o v cc 2 i/o v cc 4 i/o v cc 1 i/o v cc 3 *connect exposed pad to ground *ep + 19 20 18 17 7 6 8 i/o v l 4 en i/o v l 5 9 i/o v l 3 v cc i/o v cc 5 i/o v cc 6 i/o v cc 4 12 i/o v cc 1 45 15 14 12 11 i/o v l 1 i/o v l 2 i/o v cc 8 i/o v l 8 i/o v l 7 i/o v l 6 max3396e v l gnd 3 13 i/o v cc 3 16 10 i/o v cc 7 i/o v cc 2 tqfn *connect exposed pad to ground *ep + ucsp a b c 12 3 4 i/o v l 4 en i/o v l 2 v l i/o v l 3 i/o v l 7 i/o v l 1 i/o v l 5 max3396e i/o v cc 3 i/o v cc 7 i/o v cc 1 i/o v cc 5 d i/o v cc 4 gnd i/o v cc 2 v cc 5 i/o v l 6 i/o v l 8 i/o v cc 8 i/o v cc 6 top view (leads on bottom) top view (bumps on bottom) top view (bumps on bottom) top view (leads on bottom) pin configurations (continued)
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry 14 ______________________________________________________________________________________ selector guide part number of translators top mark max3394eeta+t 2 ape max3394eebl+t 2 aez max3395eetc+ 4 aafz max3395eebc+t 4 aco max3396eebp+t 8 max3396eetp+ 8 note: all devices specified over the -40? to +85? operating range. + denotes lead-free package. chip information process: bicmos connect exposed pad to gnd.
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry ______________________________________________________________________________________ 15 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 6, 8, &10l, dfn thin.eps common dimensions symbol min. max. a 0.70 0.80 d 2.90 3.10 e 2.90 3.10 a1 0.00 0.05 l 0.20 0.40 pkg. code n d2 e2 e jedec spec b [(n/2)-1] x e package variations 0.25 min. k a2 0.20 ref. 2.00 ref 0.250.05 0.50 bsc 2.300.10 10 t1033-1 2.40 ref 0.200.05 - - - - 0.40 bsc 1.700.10 2.300.10 14 t1433-1 1.500.10 mo229 / weed-3 0.40 bsc - - - - 0.200.05 2.40 ref t1433-2 14 2.300.10 1.700.10 t633-2 6 1.500.10 2.300.10 0.95 bsc mo229 / weea 0.400.05 1.90 ref t833-2 8 1.500.10 2.300.10 0.65 bsc mo229 / weec 0.300.05 1.95 ref t833-3 8 1.500.10 2.300.10 0.65 bsc mo229 / weec 0.300.05 1.95 ref 2.300.10 mo229 / weed-3 2.00 ref 0.250.05 0.50 bsc 1.500.10 10 t1033-2
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry 16 ______________________________________________________________________________________ 9lucsp, 3x3.eps package outline, 3x3 ucsp 21-0093 1 1 l package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry ______________________________________________________________________________________ 17 12l, ucsp 4x3.eps f 1 1 21-0104 package outline, 4x3 ucsp package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry 18 ______________________________________________________________________________________ 24l qfn thin.eps package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3394e/max3395e/max3396e qfn thin.eps package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry ______________________________________________________________________________________ 19
max3394e/max3395e/max3396e 15kv esd-protected, high-drive current, dual-/quad-/ octal-level translators with speed-up circuitry boblet maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. 5x4 ucsp.eps package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) revision history pages changed at rev 2: 1?, 9, 11, 12, 14, 20

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